Submission Format for IMS2004 (Title in 18-point Times font)

In a classical PLL, the phase detector (PD) and charge pump (CP) noise is multiplied by N, when referred to the VCO output, due to the divide-by-N in the feedback path. It often dominates the in-band phase noise and limits the achievable PLL jitter·power Figure-Of-Merit (FOM). A subsampling PLL uses a PD that sub-samples the high frequency VCO output with the reference clock. The PD and CP noise in this PLL is shown to be not multiplied by N, and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the PLL FOM, the sub-sampling PLL techniques and their applications in recent PLL architectures. Index Terms — Clock generation, clock multiplier, frequency multiplication, frequency synthesizer, phase locked loop, low jitter, low phase noise, low power, sub-sampling phase detector, sub-sampling PLL, PLL FOM.